Martin Luther University Halle-Wittenberg

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Hardware Design, Test and Verification

[We no longer work on hardware design, test and verification.]

Our Publications (1985-2013)

[33] A. Gießler, J. Ritter, and P. Molitor. Model Checking for PLC based Railway Interlocking Systems. In: Tagungsband des 16. Workshops “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pp. 71-82, Rostock, March 2013.

[32] A. Gießler, J. Ritter, and P. Molitor. BDD based analysis of test cases for PLC based railway interlocking systems. In: Tagungsband des 14. Workshops "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", S. 133-143, Oldenburg, 21.-23. Februar 2011, ISBN 978-3-00-033820-5.

[31] R. Hoffmann and P. Molitor. Guiding Property Development with SAT-based Coverage Calculation. Will appear in: Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009), August 2-5 2009, Cancun, Mexico.

[30] P. Molitor and J. Mohnke. Equivalence Checking of Digital Circuits. Kluwer Academic Publishers, Boston / Dordrecht / London, January 2004, ISBN: 1-4020-7725-4, 263 pages.

[29] M. Keim, R. Drechsler, B. Becker, M. Martin, and P. Molitor. Formal Verification of Multipliers. In: Formal Methods in System Design 22(1):39-58, Kluwer Academic Publishers, January 2003.

[28] R. Schönfeld and P. Molitor. What are the Samples for Learning Efficient Routing Heuristics? In: Proceedings of the 2002 IEEE Asia Pacific Conference on Circuits and Systems, Bali/Indonesia, October 2002.

[27] J. Mohnke, Sh. Malik, and P. Molitor. Limits of using Signatures for Permutation Independent Boolean Comparison. In: Formal Methods in System Design 21(2):98-11, September 2002.

[26] J. Mohnke, Sh. Malik, and P. Molitor. Application of BDDs in Boolean Matching Techniques for Formal Logic Combinational Verification. In: International Journal on Software Tools for Technology Transfer 3(2):207-216, Springer Verlag 2001.

[25] R. Forth and P. Molitor. Permutation Independent Comparison of Pseudo Boolean Functions. In: Notes of the International Workshop on Logic Synthesis (IWLS), pp.123-130, Dana Point, CA, May 2000.

[24] S. Wefel and P. Molitor. Prove that a Faulty Multiplier is Faulty!? In. Proceedings of the 10th Great Lakes Symposium on VLSI, GLS-VLSI, pp.43-46; Chicago, Illinois, March 2000

[23] R. Forth and P. Molitor. An Efficient Heuristic For State Encoding Minimizing The BDD Representations Of The Transition Relations Of Finite State Machines. In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference ASP-DAC, pp.61-66,Tokyo, Japan, January 2000.

[22] P. Molitor und Chr. Scholl. Datenstrukturen und effiziente Algorithmen für die Logiksynthese kombinatorischer Schaltungen. B. G. Teubner, Stuttgart / Leipzig 1999, ISBN: 3-519-02945-6, 298 Seiten.

[21] J. Mohnke, Sh. Malik, and P. Molitor. Establishing Latch Correspondence For Sequential Circuits Using Distinguishing Signatures. In: INTEGRATION, the VLSI Journal 27:33-46, 1999.

[20] Chr. Scholl, St. Melchior, G. Hotz, and P. Molitor. Minimizing OBDD Sizes Of Incompletely Specified Boolean Functions By Exploiting Strong Symmetries. In: Proceedings of the European Design and Test Conference, pp.229-234, Paris, France, March 1997.

[19] I. Peters, P. Molitor, and M. Weber. On OTC Routing With Vertical Floating Pins. In: Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems,  pp.385-388, Seoul, Korea, November 1996.

[18] P. Molitor. Recent Developments In Wiring and Via Minimization. In: Advanced Routing of Electronic Modules edited by M. Pecht and Y. Wong, pp.285-311, CRC Press, Boca Raton / New York / London / Tokyo, January 1996.

[17] Chr. Scholl and P. Molitor. Communication Based FPGA Synthesis For Multioutput Boolean Functions. In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference ASP-DAC, pp.279-287, Chiba, Japan, August 1995.

[16] I. Peters and P. Molitor. Priority Driven Channel Pin Assignment. In: Proceedings of the 5th Great Lakes Symposium on VLSI,  pp.132-135, Buffalo, New York, March 1995.

[15] Chr. Scholl and P. Molitor. ROBBD Based Computation of Common Decomposition Functions Of Multioutput Boolean Functions, In: Novel Approaches in Logic and Architecture Synthesis edited by G. Saucier and A. Mignotte, pp.57-63, Chapman-Hall 1995.

[14] B. Becker, R. Drechsler, and P. Molitor. On Generation Of Area-Time Optimal Testable Adders. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-14(9):1049-1066, September 1995.

[13] P. Molitor, U. Sparmann, and D. Wagner. Two Layer Assignment With Pin Preassignment Is Easier If Power Supply Is Already Generated. In: Proceedings of the 7th International Conference on VLSI Design, pp.149-154, Calcutta, India, January 1994.

[12] P. Molitor and Chr. Scholl. Communication Based Multilevel Synthesis For Multioutput Boolean Functions. In: Proceedings of the 4th Great Lakes Symposium on VLSI, pp.101-104,  Notre Dame, Indiana, March 1994.

[11] P. Molitor. A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization. In: INTEGRATION, the VLSI journal, 15:73-95, 1993.

[10] M. Kaufmann, P. Molitor, and W. Vogelgesang. Performance driven k-layer wiring. In: Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science (STACS), Lecture Notes in Computer Science LNCS577:489-500, Cachan, France, February 1992.

[9] B. Becker and P. Molitor. A performance driven generator for efficient testable adders. In: Proceedings of the 1st IEEE European Design Automation Conference (EURO-DAC), pp.370-375, Hamburg, Germany, September 1992.

[8] M. Kaufmann and P. Molitor. Minimal stretching of a layout to ensure 2-layer wirability. In: INTEGRATION, the VLSI journal, 12:339-352, 1991.

[7] P. Molitor. A survey on wiring. In: EIK Journal of Information Processing and Cybernetics, EIK 27(1):3-19, 1991.

[6] P. Molitor. Constrained via minimization for systolic arrays In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-9(5):537-542, June 1990.

[5] B. Becker, Th. Burch, G. Hotz, D. Kiel, R. Kolla, P. Molitor, H.-G. Osthof, G. Pitsch, and U. Sparmann. A graphical system for hierarchical specifications and checkups of VLSI circuits. In: Proceedings of EDAC’90, pp.174-179, Glasgow, Great-Britain, March 1990.

[4] R. Kolla and P. Molitor. A note on hierarchical layer assignment. In: INTEGRATION, the VLSI journal, 7:213-230, 1989.

[3] R. Kolla, P. Molitor und H.-G. Osthof. Einführung in den VLSI-Entwurf. B. G. Teubner, Stuttgart 1989, ISBN 3-519-02273-7, 352 Seiten (vergriffen).

[2] P. Molitor. On the contact minimization problem. In: Proceedings of the 4th Annual Symposium on Theoretical Aspects of Computer Science (STACS). Lecture Notes in Computer Science LNCS247:420-431, Passau, Germany, February 1987.

[1] P. Molitor. Layer assignment by simulated annealing. In: The EuroMicro Journal, Microprocessing and Microprogramming, 16:245-350, 1985.

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